1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to sophisticated metallization systems including sensitive dielectric materials and lead-free bumps or metal pillars for connecting a chip to a package.
2. Description of the Related Art
Semiconductor devices, such as microprocessors, SRAMs, ASICs (application specific ICs), systems on chip (SoC) and the like, are typically formed on appropriate substrate materials, such as silicon and the like, wherein the individual integrated circuits are arranged in an array on a wafer, so that most of the manufacturing steps, which may involve several hundred and more individual process steps in sophisticated integrated circuits, are performed simultaneously for all chip areas on the substrate, except for photolithography processes, metrology processes and packaging of the individual devices after dicing the substrate. Thus, economic constraints drive semiconductor manufacturers to steadily increase the substrate dimensions, thereby also increasing the area available for producing actual semiconductor devices and thus increasing production yield.
In addition to increasing the substrate area, it is also important to optimize the utilization of the substrate area for a given substrate size so as to actually use as much substrate area as possible for semiconductor devices and/or test structures that may be used for process control. In an attempt to maximize the useful surface area for a given substrate size, the feature sizes of circuit elements are steadily scaled down. Due to this ongoing demand for shrinking the feature sizes of highly sophisticated semiconductor devices, copper, in combination with low-k dielectric materials, has become a frequently used alternative for the formation of so-called interconnect structures comprising metal line layers and intermediate via layers that include metal lines as intra-layer connections and vias as inter-layer connections, which commonly connect individual circuit elements to provide the required functionality of the integrated circuit. Typically, a plurality of metal line layers and via layers stacked on top of each other is necessary to implement the connections between all internal circuit elements and I/O (input/output), power and ground pads of the circuit design under consideration.
For extremely scaled integrated circuits, the signal propagation delay is no longer limited by the circuit elements, such as field effect transistors and the like, but is limited, owing to the increased density of circuit elements requiring an even more increased number of electrical connections, by the close proximity of the metal lines, since the line-to-line capacitance is increased, in combination with a reduced conductivity of the lines, due to a reduced cross sectional area. For this reason, traditional dielectrics such as silicon dioxide (k>4) and silicon nitride (k>7) are replaced by dielectric materials having a lower permittivity, which are, therefore, also referred to as low-k dielectrics, having a relative permittivity of 3 or less. However, the density and mechanical stability or strength of the low-k materials may be significantly less compared to the well-approved dielectrics silicon dioxide and silicon nitride. As a consequence, during the formation of the metallization system and any subsequent manufacturing processes of integrated circuits, production yield may depend on the mechanical characteristics of these sensitive dielectric materials and their adhesion to other materials.
In addition to the problems of reduced mechanical stabilities of advanced dielectric materials having a dielectric constant of 3.0 and significantly less, device reliability may be affected by these materials during operation of sophisticated semiconductor devices due to an interaction between the chip and the package caused by a thermal mismatch of the corresponding thermal expansion of the different materials. For instance, in the fabrication of complex integrated circuits, increasingly a contact technology may be used in connecting the package carrier to the chip, which is known as flip chip packaging technique. Contrary to the well-established wire bonding techniques in which appropriate contact pads may be positioned at the periphery of the very last metal layer of the chip, which may be connected to corresponding terminals of the package by a wire, in the flip chip technology, a respective bump structure may be formed on the last metallization layer, for instance using aluminum as a terminal metal, in combination with a solder material which may be brought into contact with respective contact pads of the package. Thus, after reflowing the bump material, a reliable electrical and mechanical connection may be established between the terminal metal formed on the last metallization layer and the contact pads of the package carrier. In this manner, a very large number of electrical connections may be provided across the entire chip area of the last metallization layer with reduced contact resistance and parasitic capacitance, thereby providing the IO (input/output) capabilities, which may be required for complex integrated circuits, such as CPUs, storage memories and the like. During the corresponding process sequence for connecting the bump structure with a package carrier, a certain degree of pressure and/or heat may be applied to the composite device so as to establish a reliable connection between each of the bumps formed on the chip and the bumps or pads that may be provided on the package substrate. The thermally or mechanically induced stress may, however, also act on the lower lying metallization layers, which may typically include low-k dielectrics or even ultra low-k (ULK) dielectric materials, thereby significantly increasing the probability of creating defects in the form of cracks, delamination and the like, due to the reduced mechanical stability and adhesion to other materials.
Moreover, during operation of the finished semiconductor device attached to a corresponding package substrate, significant mechanical stress may occur due to a significant mismatch in the thermal expansion behavior of the silicon-based semiconductor chip and the package substrate, since, in volume production of sophisticated integrated circuits, economic constraints typically require the use of specified substrate materials for the package, such as organic materials, which typically may exhibit a different thermal conductivity and a coefficient of thermal expansion compared to the silicon chip.
With reference to FIGS. 1a-1b, a typical configuration of a semiconductor device including a solder bump structure for flip chip connection will now be described in more detail.
FIG. 1a schematically illustrates a top view of the configuration or layout of a semiconductor device 100 in which the mechanical and electrical connection between a package and the device 100, i.e., a specific chip or die 101, is to be established on the basis of a solder bump structure, or in sophisticated cases a metal pillar structure. For this purpose, an appropriate distribution of contact elements 110, which will also be referred to herein as chip or die contact elements, across the entire area of the die 101 may be provided, wherein, as previously discussed, nearly the entire area of the die 101 is available for appropriately positioning the contact elements 110. In this manner, a very complex chip-package contact structure may be accomplished, wherein each of the contact elements 110 may be connected to a counterpart contact pad or bump of a corresponding package substrate during a single manufacturing process, contrary to corresponding wire bond techniques in which a bond wire may have to be connected to bond pads of the chip and the package in a substantially sequential manner.
FIG. 1b schematically illustrates a cross-sectional view of the device 100 according to the line Ib in FIG. 1a. As illustrated, the device 100 comprises the die or chip 101, which may be understood as the basic substrate for forming thereabove circuit elements and the like. The substrate 101 is typically provided in the form of an insulating substrate, a semiconductor material and the like. It should be appreciated that, in and above the substrate 101, typically, a plurality of circuit elements, such as transistors, capacitors, resistors and the like, are provided in accordance with the circuit function to be implemented in the device 100. For convenience, any such circuit elements, which may include elements with critical dimensions of 50 nm and less in sophisticated devices, are not shown in FIG. 1b. As discussed above, due to the complex layout of electronic circuits implemented in the semiconductor device 100, a complex metallization system 120 is typically required, which may comprise a plurality of metallization layers stacked on top of each other, wherein, for convenience, a metallization layer 130 and a metallization layer 140 are depicted. For instance, the metallization layer 130 may be comprised of a dielectric material 131, such as a low-k dielectric material, a ULK material and the like, in which metal lines and vias 132 are embedded that are typically comprised of copper, in combination with appropriate conductive barrier materials so as to provide a reliable copper confinement. It should be appreciated that not necessarily each metallization layer of the system 120 may comprise a sensitive low-k dielectric material since different metallization levels may require different performance characteristics, for instance with respect to drive current capability and signal propagation delay. However, at any rate, typically, a plurality of metallization layers may comprise a sensitive low-k dielectric material, thereby reducing the overall mechanical stability, as discussed above. Furthermore, the metallization layer 140 represents the “last” metallization layer and comprises any appropriate dielectric material 141 including metal regions 142, which may represent contact pads for connecting to a contact structure or bump structure 150, which may actually represent the interface for connecting the device 100 with a package substrate (not shown). The contact or bump structure 150 typically comprises a passivation layer 151, which may thus passivate the metallization system 120, wherein, typically, a plurality of dielectric materials, such as silicon dioxide, silicon oxynitride and silicon nitride, are used to provide the desired characteristics in view of chemical and mechanical stability. Moreover, a further dielectric material, such as a polyimide 152, is formed on the passivation material 151. The materials 151 and 152 are patterned in such a way that an opening 150A is aligned to at least a portion of the contact pad 142 of the last metallization layer 140. As explained before, in sophisticated metallization systems, such as the system 120, copper is preferably used which, however, may not be compatible with well-established process techniques and materials as have been used in complex metallization systems formed on the basis of aluminum. For this reason, frequently, a further metal material 153, which is also referred to as a terminal metal, in the form of aluminum, is provided so as to act as an interface between the sensitive copper material of the pad 142 and the contact element 110. In this manner, well-established materials and techniques may be applied for forming the contact element 110, for instance by providing efficient underbump metallization systems 154, for instance based on chromium, copper, tungsten and the like.
In other cases, the contact structure 150 may be formed on the basis of copper metals including any appropriate barrier materials without requiring specific terminal metals, such as the material 153.
The semiconductor device 100 comprising the metallization system 120 may be formed on the basis of the following processes. After completing any semiconductor-based circuit elements, such as transistors and the like, the one or more metallization layers 130, 140 may be formed by providing a material layer and layer stack, which, as discussed above, may comprise extremely sensitive materials, which may then be patterned on the basis of sophisticated lithography techniques and anisotropic etch processes. Thereafter, appropriate barrier materials and copper-based materials may be deposited, for instance in sophisticated dual inlaid techniques, in which vias and metal lines may be filled in a common deposition process. Thereafter, any excess material may be removed, for instance, by chemical mechanical polishing (CMP), wherein a certain mechanical stress may be induced in the sensitive dielectric materials, which may also contribute to a certain degree of deterioration of the mechanical stability of these materials. After completing the metallization layers 130, 140, further complex process techniques may be applied so as to provide the contact structure 150 including the deposition and patterning of the various materials in accordance with the device requirements. After providing the opening 150A, typically, a deposition mask is applied and an appropriate solder material may be deposited and appropriately treated so as to form the contact element 110. In other process strategies, an appropriate metal pillar may be provided in the opening 150A so as to extend above the dielectric layer 152 with a desired height and lateral dimensions, wherein typically an increased contact density may be possible by using appropriate metal pillars, compared to solder bumps.
After separating the semiconductor device 100 into individual chips or dies 101, a connection to an appropriate package substrate may be accomplished by mechanically coupling an individual device 101 and the corresponding package substrate and reflowing the contact elements 110, thereby obtaining the desired intermetallic connection between the contact elements 110 and the corresponding contact pads of the package substrate, which may also comprise a bump structure, depending on the overall process strategy. Finally, any appropriate fill material may be provided between the chip 101, i.e., the contact structure 150, and the package substrate so as to enhance mechanical, chemical and thermal stability of the composite device.
As discussed above, during the fabrication of the semiconductor device 100 and also during the process of connecting the individual chips 101 with a package substrate and in particular during operation of the packaged semiconductor device, significant mechanical stress may be applied to the metallization system 120 via the contact structure 150, i.e., via the contact elements 110. In prior contact technologies, a certain degree of resilience of the contact elements 110 has resulted in a certain degree of buffer effect, due to a significant amount of lead in the composite solder material. Upon introducing so-called lead-free solder materials, however, for instance in view of environmental regulations and the like, and also in an attempt to further improve the thermal and electrical performance of the contact structure 150, for instance by providing copper pillars instead of using bump structures, the mechanical stress in the metallization system 120 may be significantly increased, since typically these materials, and in particular the pillar structures, may be stiffer compared to the lead-containing solder materials, thereby transferring significantly increased shear forces into the metallization system 120 and in particular into the last metallization layer 140. For these reasons, in many conventional approaches, the increase of the mechanical stress in the metallization system 120 may require a reduction in complexity, in terms of providing dielectric materials of superior mechanical stability, thereby, however, typically increasing the dielectric constant and thus reducing the overall electrical performance of the metallization system 120. Thus, monitoring the mechanical characteristics of the sophisticated low-k dielectric materials is an important aspect for complex semiconductor devices, so that conventionally a corresponding process control may be established, in which, in particular, the characteristics of low-k materials may be monitored, for instance by determining several material characteristics after the deposition of these materials.
As discussed above, the material characteristics of low-k dielectric materials as such may represent only one aspect that influences the finally obtained mechanical characteristics of a complex metallization system. Another factor is to be seen in the process history, i.e., the various complex manufacturing processes, which may also influence adhesion and other characteristics of the sensitive materials, which may also finally result in a deterioration of the overall mechanical stability of complex metallization systems. Moreover, the complex interaction of the several layers and materials in a complex metallization system are not appropriately taken into consideration upon monitoring the material characteristics of individual low-k dielectric material layers, thereby resulting in less reliable assessments of metallization systems in terms of reliability upon connecting semiconductor devices to a package and operating a packaged semiconductor device.
The present disclosure is directed to various methods and systems that may avoid, or at least reduce, the effects of one or more of the problems identified above.